This invention relates generally to increasing computer performance, and more particularly to a method and apparatus for exploiting underutilized or stalled execution cycles in the normal instruction stream by performing memory block initialization during processing stalls or idle memory write periods.
Increasing computing speed and efficiency is a continual and tireless effort. The increasing complexity of application programs, greater need for networking capabilities, and the advent of the worldwide web are but a few computing categories begging for faster processing rates. As is known, there is a practical limit at any implementation to raw clock speeds, and innovative processing arrangements and methodologies often prove to be the key to unlocking further processing speed bottlenecks.
In order to increase processing speeds, many useful processing arrangements and methods have been devised. Multiprocessing, multitasking, pipelining, data bursting and many other technological advances have allowed processing speeds to increase. Despite these advances, certain conditions within the computing system can cause significant delays or otherwise waste valuable processing time. For example, during instruction execution by a processor, the processor encounters periods when it is not accomplishing useful work. This can occur for a variety of reasons, including data dependencies, memory latencies, changes in program flow, etc. The exploitation of these idle periods can significantly increase computing speed and data throughput.
Out-of-order instruction execution is one prior art manner of exploiting idle processor times and consequently increasing the ratio of working/idle processor time. Out-of-order instruction execution is very complex, however, and the complexity increases as the number of asynchronous events that must be recovered increases. Furthermore, processing xe2x80x9cstallsxe2x80x9d, wasted instruction execution, and idle memory write periods can still occur in such an environment.
Running multiple instruction streams is another manner that attempts to take advantage of processing stalls. While some hardware may be shared, this solution may still require additional resources. The complexity is increased due to the need to coordinate the multitasking environment to properly utilize processing stalls, thereby increasing complexity and cost of the system. Further, these methods do not take advantage of available resources other than processing stalls in the instruction stream.
Therefore, it would be desirable to provide a system and method for increasing overall processing speeds by making use of periods of inactivity, without introducing the complexities and unpredictable results associated with other methods, such as out-of-order instruction execution or pure software methods. The present invention provides a solution to this problem by exploiting underutilized processor execution cycles and idle memory write cycles, and asynchronously performing certain activities in the background. The present invention therefore provides a solution to the aforementioned and other problems, and offers other advantages over the prior art.
The present invention relates to a system and method for increasing processing performance by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods.
In accordance with one embodiment of the invention, a method is provided for increasing processing performance in a computer system. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, and the inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles.
In accordance with another embodiment of the invention, a method for increasing processing performance in a computer system is provided. The computing system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data pages in the memory are identified, and a first list of first addresses corresponding to the identified inactive data pages are stored in a first linked list. Idle memory write cycles associated with a data write interface between the instruction processor and the memory are identified. The inactive data pages associated with the list of addresses are cleared to a predetermined state during the identified idle memory write cycles. The instruction processor initiates this clearing function via the data write interface, and this activity is independent of activity in the instruction stream. A second list of second addresses corresponding to the inactive data pages that have been cleared is stored in a second linked list.
In accordance with another embodiment of the invention, a system for asynchronously initializing inactive data blocks in a computing system is provided. A memory stores instructions and data associated with an instruction stream, where the memory includes inactive data blocks currently unused by the computing system. These inactive data blocks have residual data that is to be cleared before further use. A first queue stores addresses corresponding to the inactive data blocks, and a second queue stores addresses corresponding to the inactive data blocks that have been initialized. At least one instruction processor is provided to process the instruction stream, where the instruction processor includes a write interface coupled to the memory to allow data to be written to the memory. The instruction processor accepts the addresses from the first queue, initializes the corresponding inactive data blocks via the write interface during idle memory write cycles between the instruction processor and the memory, and stores the addresses corresponding to the inactive data blocks that have been initialized onto the second queue.
Another embodiment of the invention provides a system for asynchronously initializing inactive data blocks in a computing system. The system includes a memory for storing instructions and data associated with an instruction stream, where the memory includes inactive data blocks currently unused by the computing system. The memory also includes a first linked list to store addresses corresponding to the inactive data blocks, and a second linked list to store addresses corresponding to the inactive data blocks that have been initialized. At least one instruction processor is provided to process the instruction stream, and includes a write interface coupled to the memory to allow data to be written to the memory. The instruction processor is configured and arranged to accept the addresses from the first linked list, initialize the corresponding inactive data blocks via the write interface during idle memory write cycles between the instruction processor and the memory, and to store the addresses corresponding to the inactive data blocks that have been initialized onto the second linked list.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modification without departing from the scope and spirit of the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.